A commonly used method for forming metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys. Excess copper on the surface of the dielectric layer is then removed by a chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal lines.
Copper is preferred in interconnect structures because of its low resistivity. However, copper suffers from electro-migration (EM) and stress migration (SM) reliability issues as geometries continue to shrink and current densities continue to increase.
FIG. 1 illustrates a cross-sectional view of an intermediate stage in the formation of a conventional interconnect structure. Copper line 4 is formed in low-k dielectric layer 2. Etch stop layer (ESL) 6 is formed on the top surface of copper line 4 and low-k dielectric layer 2.
One of the concerns of the interconnect structure shown in FIG. 1 is its reliability, which may be measured using time dependent dielectric breakdown (TDDB). The TDDB is affected by the electro-migration of copper in the interconnect structure. The electro-migration of copper causes copper atoms to migrate from portions of the interconnect structure to others, and hence causing voids. This not only increases the RC delay of the interconnect structures, but also eventually leads to open circuits. This is particularly true for integrated circuits formed using advanced technologies, for example, 32 nm and below. At such low scales, the poor interface between copper and overlying etch stop layer causes interconnect structures to have poor resistance to electro-migration.
The methods for reducing electro-migration were previously explored. These methods include, for example, forming metal caps on copper lines, wherein the metal caps are typically formed of CoWP. These methods generally have tradeoffs, such as increased manufacturing cost. New methods for improving the interconnect structures' resistance to electro-migration are thus needed.